My first CPU was the 6502, but even to me the animation of its operation on visual6502.org looks confusing. I looked into theory, but don't feel like I have something to contribute to the abstractions. Since I know physics and heard of Spice, I thought that I could animate the circuit more fluently using a physically motivated simulation of the nMOSFET logic in the 6502. I simplified the CPU a bit (so lied, abstractions incoming!). Other 8 bit CPUs had more registers. This allows a load-store architecture, which is easier to follow. 8-bit CPUs already had a 16 bit address bus. I want to try out a 16 bit ALU for efficient address calculations and register based maths. Then I compare it to multi-cycle operation on smaller ALUs and see how many transistors this will save. The ALU is split into two phases. The carry is cleared and set by feeding operands, so that I can avoid a gate in the loop.
Of course, for toy problems, I only need 8 bit addresses. I can easily show 8 bit code and data memory on a full-HD screen. Logisim could possibly also calculate gate delays. Just a physical simulation naturally explains slow down due to fan out, and tell us if transients from different paths length are gobbled up by the finite transition times of single transistors. I want a fully static design driven by two non-overlapping phases. Then I check if there is any part in a CPU which would profit from a dynamic and async design.I know two ways to tune a static design. For one, active pull ups (pre-charge) can speed up the design. But I always want to also keep the static pull-ups. With equal path length through the combinatorial circuits, at the clock limit, the phases can be made to overlap, to achieve a little high clock rates.
Click image to restart animation where conductivity is increased. Green is electric potential. Violet is carrier density. Vgs increases top to middle, then decreases again to bottom. Starting at 9, simulated time per step increases.
I learned that this is called 1 dimensional device Technology Computer-Aided Design. Bipolar transistors were simulated in one dimension because they are homogenous in the other. Due to temperature and the particle nature (?) real FETs have a channel width. But I use classic electron density in a channel ( like hetero-junction laser diode or finfet ). I simulate the field along the channel to (in turn) simulate pinch-off. Still unsure about this. It is just a parameter. I don't show channel depth on screen ( or carrier profile). I don't show the elctric field in the depletion zone of the body diode .. or do I ? At least I don't plan to use it for simulation. I will just interpolate linearly from channel to body. The body diode may be interesting because I found that the simulation really likes to simulate CCD and charge pumps. So the body diode may begin to conduct. But this serves no purpose in my design. And I could always fall back to the design without said diode. Increase bandwidth. FinFet all around. Fnterestingly, for CMOS, I need to set the body voltage into the middle of the rails. So, the bandgap is kinda important? Ah this is what they say that in modern cores with rail voltage < the bandgap, there is not parasitic thyristor anymore. They can just connect the body to the middle voltag. For the shell, the N and P body ( strips? ) are connected to the rails opposed to the source rail.
Electrons live on a wire, think of carbon nanotube. Or a thin film of silicon on silicon Oxide. Vacuum on the other side? I dunno about surface states. I feel like a finFET is actually most easy to simulate. Molecular film of silicon between two sliced of SiO2. I still only display on electrode for clarity.
Signal MOSFETS are of enhancement mode. So I don't need doping. I don't simulate the source in detail, but as Ohmic resistance. The pull-up transistors have a ferroelectric between insulation and the metal gate. This acts like doping, but without catching charge carriers at low temperature. Multiple gates along the channel to implement a charge coupled device.
Electrons are displayed as blue typically. For the voltage I could use green. I use a simple geometry. Red could mean bandgap. The gate insulation is a red line. But I don't need crimson in the channel. Channel is know by geometry, it is the continous thing connected on the extreme sides, while the metal gates sit in a row and come from the short side. There do exists some MOSFET symbols with a broken channel and emphasis on the body diode. This is just futile here. Pull-ups use the same color. You recognize them by the short between electrode and first gate. Maybe here I should use a gate on the other side of the short-cut gate. Maybe even use a series of two gates with fixed charge to adjust the pull-up characterisitic. The first gate with its captured charge set the threshold voltage so that this transistor always leaks when source=gate. The second gate in a physical transistor is used to reduce (parasitic) capacity. Only very few charge carriers live here (saturation region = pinch off). Other transistors also saturate with positive voltage on the gate. So this is interesting for the simulation.
Each gate is composed of 4 micro-gates for a nice animation. Between gates, I don't simulate a gap. I don't think that anyone will notice. In the Ohmic region the charge on these capacitors is proportional to V_GS . The a slight V_DS pulls on those charge carriers, which then exhibit friction, which leads to a fixed velocity. Now with pinch-off, the carriers come in dynamically from a cell on the side. Voltage pulls on them. No equilibrium is reached. Speed is still limited by friction. In the saturation region, current is higher than in the Ohmic region. So velocity over compensates for lower carrier density. I am not sure about electric field simulation. Do I need a constant field? So at each cell = micro capacitor we have the voltage across the dielectic. The gate locally delivers electrons as needed. A global shortage affects the global voltage and pulls on the impedance of the coax cable connected to it.
But in the semiconductor, charge is slow to compensate this. So on pinch off there is trough. But negative charge in the gate compensates this to some degree given its local capacity. I need some magic values for my simlulation. Let's start with charge on the gate that is only half as effective? Negative charge gathers in gate, voltage accross dielectric is halved, divergence of field in channel is also halved. With gates on both sides, this series capacitor and charged used up by it is calculated in one step (other gate replaces ferrorelectric gate), then semiconductor simulation only sees net field. The floating insulated gate does not pull on any cable. Now it occurs to me that any gate needs a capacitity towards GND. It is hard to imagine that it is lower than through the gate dielectric. Lets say: For one charge carrier (gates are bipolar as a metal, but only compensate channel charge in my application) per two cells, voltage changes by 1.
The gate capacity is needed to stabilize the simulation, but it can by very high because I can always slow down the simulation and let the cables do their work. I do care for fan-out. Should I start with a fixed voltage on the gate? Strict voltage follow on the coax (with implied, matched termination?).
2D simulation might be interesting to zoom in, to explain the bulk diode, or to simulate electron beams in a vacuum tube.
Insulator
Color Codes for the fild (left image ): red=insulator, blue = charge density